The present invention relates generally to practical “back end” thin film capacitor structures and methods, and also to integrating such back end thin film capacitors into processes and methods for making “back end” thin film resistors. (The term “back end” is used herein to describe integration of components, including thin film capacitors and back end thin film resistors, onto a partially fabricated integrated circuit structure after transistors and polycrystalline silicon structures have already been formed therein. So-called “front end” processes typically include steps performed at a temperatures of 600 to 700 degrees Centigrade, whereas at the present state-of-the-art, “back end” processes typically include only steps performed at temperatures less than roughly 450 degrees Centigrade.)
FIG. 1 shows a prior art structure in which various transistors have been formed, using conventional techniques, in a region 4 of a starting silicon substrate 1. A standard pre-metal dielectric layer 2 formed on silicon substrate 1 includes a first TEOS (tetraethyl orthosilicate) sublayer on the silicon substrate 1, a BPTEOS (Boron-Phosphorus TEOS) sublayer on the first TEOS sublayer, and a second TEOS sublayer on the BPTEOS sublayer. A thin layer 3 of sichrome (SiCr), having a sheet resistance typically in the range from 30 to 2000 ohms per square (based on previously developed curves of TCR versus sheet resistance for the particular SiCr deposition process) has been deposited on the upper surface of pre-metal dielectric layer 2. A conventional photoresist deposition, etching, and cleaning process has been performed to define the shape of SiCr resistor 3. A standard TEOS barrier layer 5 is formed on the upper surfaces of pre-metal dielectric layer 2 and SiCr resistor layer 3. A thin layer 6 of nichrome (NiCr) having a sheet resistance, typically in the range of 30 to 2000 ohms per square has been deposited on the upper surface of TEOS barrier layer 5, and a layer 9 of TiW has been formed and patterned on nichrome layer 6. After performing a photoresist procedure to define the locations of contact openings, such as contact opening 7, to expose electrodes/terminals of various other elements such as transistors and diffused resistors in region 4, such contact openings 7 have been etched through TEOS layer 5 and pre-metal dielectric layer 2 and a contact opening 10A has been etched through TEOS barrier layer 5 to expose a contact area of sichrome layer 3, as illustrated. Then a first metallization layer, referred to as the “Metal 1” layer, has been deposited on the exposed surface of the wafer and appropriately patterned to provide the structure including sections 12A, 12B and 12C as shown in FIG. 1.
Section 12A of Metal 1 layer fills contact opening 7, making good electrical contact to an electrode of a transistor or other element in region 4. Metal 1 section 12A also fills a SiCr resistor via opening 10A to electrically contact SiCr resistor 3. Metal 1 section 12B extends over most of the area of sichrome resistor 3 to form the upper plate of a back end capacitor, the lower plate of which is formed by sichrome layer 3, with TEOS barrier layer 5 between them to form the capacitor dielectric. Metal 1 section 12B also contacts one end of nichrome resistor 6, the other end of which is contacted by Metal 1 section 12C, as shown. The TiW material 9 provides improved electrical contact to the NiCr.
Back end capacitors of the type shown in FIG. 1 typically require a large amount of chip area. For state-of-the-art “deep submicron” technologies having 45-90 nanometer line widths in which trench isolation and dummy devices, CMP (chemical mechanical polishing), dummy fill to avoid “dishing”, and a particular periodicity of back end thin film resistor lines are required, such back end capacitors may need to be made larger as the line widths get smaller because the back end capacitors may need to be constructed of multiple unit capacitor cells in order to be compatible with the minimum line widths and required periodicity.
Design engineers have endeavored to develop optimized back-end thin film resistor structures having various sheet resistances and TCRs (temperature coefficients of resistance) in single integrated circuits by controlling the thermal cycles to control the sheet resistances and TCRs of multiple back end thin film resistors formed on successive oxide layers.
“Poly-capacitors”, including poly-oxide-metal and poly-oxide-poly capacitors are well-known in the art, but are not considered to be suitable as “back end” capacitors because they must be formed in conjunction with formation of the transistors and therefore “compete” with the transistors for unavailable chip area. (The term “poly” is used herein to refer to doped polycrystalline silicon.) Such poly capacitors have a number of shortcomings as a result of the characteristics of doped polycrystalline silicon layers, including relatively low capacitance per unit area because the oxide dielectric is usually relatively thick. Another shortcoming is that the voltage coefficients of poly capacitors may be variable as a function of the voltage between the capacitor plates.
In some cases it would be desirable to be able to provide back end capacitors in integrated circuits with already-formed integrated circuit substructures including transistors and/or other integrated circuit elements such as diffused resistors and/or polycrystalline silicon resistors. Also, it would be desirable to have a practical way of providing capacitors and resistors in integrated circuits which do not “compete” for chip area used for providing transistors, in contrast to use of conventional polycrystalline silicon resistors and capacitors which do compete for chip area used for providing transistors. Furthermore, it would be desirable to have a relatively simple manufacturing process which allows the option of providing one or more different kinds of back end capacitor structures having different characteristics within a single integrated circuit.
There is an unmet need for an improved integrated circuit structure and method for integrating one or more different kinds of back end capacitor structures into integrated circuits with already-formed integrated circuit substructures including transistors and/or other integrated circuit elements such as diffused resistors and/or polycrystalline resistors.
There also is an unmet need for an improved integrated circuit structure and method for integrating back end capacitors into integrated circuits with already-formed integrated circuit substructures including transistors and/or other integrated circuit elements such as diffused resistors and/or polycrystalline resistors using the same manufacturing process utilized for integrating back end thin film resistors into such integrated circuits.
There also is an unmet need for a practical way of providing capacitors and/or resistors in integrated circuits which do not “compete” for available chip area in which transistors can be formed.